********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Jul 14, 2014
*ECN S14-1411, Rev. B
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si2323CDS D G S 
M1 3 GX S S PMOS W= 1485600u L= 0.25u 
M2 S GX S D NMOS W= 1485600u L= 4.057e-07 
R1 D 3 1.444e-02 6.499e-03 3.146e-06 
CGS GX S 1.802e-10 
CGD GX D 1.000e-13 
RG G GY 4.1
RTCV 100 S 1e6 5.420e-05 -1.336e-06 
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 
**************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 1.7e-8 
+ RS = 1.151e-02 KP = 8.148e-06 NSUB = 3.329e+14 
+ KAPPA = 1.421e-04 ETA = 1.000e-07 NFS = 2.085e+11 
+ LD = 0 IS = 0 TPG = -1) 
*************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 1.7e-8 
+NSUB = 6.092e+16 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.585e-08 TREF = 25 BV = 22 
+RS = 3.396e-02 N = 1.308e+00 IS = 3.537e-08 
+EG = 5.000e-01 XTI = 1.000e+01 TRS = 1.000e-05 
+CJO = 1.889e-10 VJ = 4.932e-01 M = 7.265e-01 ) 
.ENDS 
